Attention is focused to a magnetic random access memory (MRAM) as a nonvolatile memory that can carry out a write operation and a read operation in a high speed and has a large number of times of rewrite.
A memory cell of the MRAM has a tunneling magnetic resistance (hereafter to be referred to as Tunneling Magnetic Resistance: TMR), which includes a magnetic layer (pinned layer), a magnetic layer (free layer), and an insulating layer, as a memory unit. The pinned layer has a fixed spontaneous magnetization. The free layer has a reversible spontaneous magnetization. The free layer is formed so that the direction of the spontaneous magnetization of the free layer becomes parallel or anti-parallel with the direction of the spontaneous magnetization of the pinned layer. The insulating layer is put between the above two layers.
The memory cell stores 1-bit data in accordance with the direction of the spontaneous magnetization of the free layer to the direction of the spontaneous magnetization of the pinned layer. For example, the memory cell can take the following two states: a parallel state (a first state) in which the direction of the spontaneous magnetization of the free layer and the direction of the spontaneous magnetization of the pinned layer, and an anti-parallel state (a second state) in which the direction of the spontaneous magnetization of the free layer and the direction of the spontaneous magnetization of the pinned layer are opposite to each other. In this case, the 1-bit data is stored by relating one of the parallel state and the anti-parallel state to “0” and the other of them to “1”.
The directions of the spontaneous magnetizations of the free layer and pinned layer influence the resistance of the memory cell. Here, it is assumed that the resistance of the TMR when directions of the spontaneous magnetizations of the free layer and pinned layer are parallel is R0. In this case, if the directions are anti-parallel, the resistance of the TMR becomes R0+ΔR. The ΔR/R0 (%) is generally referred to as an MR ratio. The MR ratio normally ranges between 10 and 50%. That is, the data stored in the memory cell can be determined by detecting the resistance value the TMR corresponding to directions of the spontaneous magnetizations of the free layer and pinned layer. The resistance value of the TMR is detected in accordance with the following method. For example, a predetermined voltage is applied to the both ends of the TMR to detect current flowing through the TMR, i.e., sense current. Otherwise, a voltage appearing at the both ends of the TMR, i.e., a sense voltage is detected by supplying a predetermined current to the TMR.
FIG. 1 is a block diagram showing a typical configuration of an MRAM.
As shown in FIG. 1, a memory cell 103 is configured by connecting a TRM 109 with an access transistor 110 in series. One terminal of the TMR 109 is connected to a bit line 105a and the source terminal of the transistor 110 is connected to ground 111. A plurality of memory cells 103 are arrange like a matrix. Similarly, a reference memory cell 104 is configured by connecting a reference TMR 108 and an access transistor 112 in series. One terminal of the reference TMR 108 is connected to a reference bit line 105b and the source terminal of the transistor 112 is connected to the ground 113. A plurality of reference memory cells 104 are arranged along the reference bit line 105b. Moreover, the memory cells 103 arranged like a matrix and the reference memory cells 104 arranged along the reference bit line 105b form a memory cell array 120.
In this case, the transistor 110 of the selected memory cell 103 is turned-on. Moreover, the bit line 105a selected by a Y selector 102 is connected with a read circuit 101. The transistor 112 of the selected reference memory cell 104 is turned-on. Moreover, the bit line 105b selected by the selector 102 is connected with the read circuit 101. The read circuit 101 compares a signal from the selected bit line 105a with a signal from the selected reference bit line 105b to carry out a read operation.
A method for reading the data stored in a memory cell will be described in detail by using a first conventional example (U.S. Pat. No. 6,392,923). In this case, it is defined that a state in which a TMR is parallel is “0” (TMR resistance value is R0) and a state in which the TMR is anti-parallel is “1” (TMR resistance value is R1=R0+ΔR).
FIG. 2 is a block diagram showing a configuration of a reference memory cell and its periphery. The data stored in the memory cell 103 is read out by detecting the previously described sense current or sense voltage by the read circuit. Moreover, a reference current or reference voltage for determining whether the sense current or sense voltage is kept at “0” or “1” is necessary. In case of the reference memory cell 104a shown in FIG. 2, two sets of one TMR storing “0” and one TMR storing “1” connected in series are connected in parallel in order to generate a reference signal. In this case, the reference value Rref of the reference cell is shown by the following equation (2).Rref=(R0+R1)/2  (2)The resistance value of the reference memory cell 104a logically takes a value between R0 and R1. That is, it is possible to generate a reference signal suitable to determine the data stored in the memory cell 103.
FIG. 3 is a graph showing a relation of voltage (both-end voltage) applied between both ends of a TMR and MR ratio. The vertical axis denotes MR ratio (%) and the horizontal axis denotes both-end voltage (V) of TMR. The MR ratio of the TMR depends on magnitude of the both-end voltage (V) of the TMR in accordance with the influence of the bias dependency peculiar to the TMR element shown in FIG. 3.
With reference to FIG. 3, an actual reference signal becomes a value close to a sense signal of “1” in case of the method disclosed in the first conventional example. As shown in FIG. 3, the MR ratio of the TMR decreases as its both-end voltage rises. A voltage applied between the both ends of each TMR in the reference memory cell 104a in the above U.S. Pat. No. 6,392,923 (FIG. 2) is about ½ of the voltage applied between the both ends of the TMR of the memory cell 103. Therefore, as a result of comparison with the RM ratio of the TMR in the memory cell 103, the MR ratio of the TMR in the reference memory cell 104a increases. Thus, the reference signal is shifted in a direction of the sense signal of “1” from the intermediate value of the sense signal between “0” and “1”. When the shit is present in the TMR resistance value, there is a possibility that the reliability in the read operation is greatly impaired. In this case, to improve the reliability in the read operation by the method according to the above first conventional example, it is necessary to carry out a control so as for voltages to be equally distributed to the both ends of TMRs in the memory cell 103 and reference memory cell 104a. 
Also, in the method according to the above U.S. Pat. No. 6,392,923, four TMR elements are necessary for the reference memory cell 104a. When a resistance variation of a TMR is compensated by providing a column of reference memory cells in the memory cell array 120, the rate of the area occupied by the reference memory cells 104a increases. Moreover, when a short-circuited TMR produced due to a defect at the time of manufacturing is included in the reference memory cell 104a, a word line defect is caused that it is impossible to read the memory cells 103 on a read word line 107. A probability of the word line defect increases because of the fact that the reference memory cell 104a has the four TMRs. Moreover, the resistance value and MR ratio of a TMR are decreased due to a temperature rise.
A technique is demanded capable of determining a data stored in a memory cell of an MRAM in a high reliability. A technique is demanded of a read circuit capable of determining the data stored in the memory cell of the MRAM in the high reliability, while suppressing the increase of a chip area. A technique is demanded of the read circuit capable of determining the data stored in the memory cell of the MRAM in the high reliability without depending on a MR ratio and the resistance value of a TMR. A technique is demanded in which a reference signal in the memory cell of the MRAM takes an intermediate value between the sense signal of “0” and the sense signal of “1” without depending on the MR ratio and the resistance value of the TMR.
In conjunction with the above description, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-P2002-222589A). This semiconductor device is provided with a plurality of first memory cells, a plurality of first dummy cells, and a plurality of second dummy cells. The plurality of first memory cells are provided at intersections of a plurality of word lines and a plurality of first data lines to store either of first data or second data. The plurality of first dummy cells is provided at intersections of the plurality of word lines and a plurality of first dummy data lines to store the first data. The plurality of second dummy cells are provided at intersections of the plurality of word lines and a plurality of second dummy data lines to store the second data. Moreover, the semiconductor device is further provided with a first multiplexer, a second multiplexer, a read circuit, a first common data line, and a second common data line. In this case, the fist multiplexer is connected to a plurality of first data lines. The second multiplexer is connected to the fist and second dummy data lines. The read circuit is connected to the first and second multiplexers. The first common data line connects the read circuit with the first multiplexer. The second common data line connects the read circuit with the second multiplexer. The read circuit includes a first current mirror circuit, a second current mirror circuit, a first sense data line, a second sense data line, and a sense amplifier. In this case, the first current mirror circuit is connected to the first common data line. The second current mirror circuit is connected to the second common data line. The first sense data line is connected to the first current mirror circuit. The second sense data line is connected to the second current mirror circuit. The sense amplifier is connected to the second sense data line.
Also, an evaluation apparatus for a cell resistance in a magnetic resistance memory is disclosed in Japanese Laid Open Patent application (JP-P2002-541608A) (International Application No. PCT/DE00/00778). In the evaluation apparatus for the cell resistance in the magnetic resistance memory, a first terminal of each cell resistance (R) is connected to a word line voltage (VWL) through a switch (US). Also, a second terminal of each cell resistance is connected to a line node (L) through another switch (S). The line node (L) is connected to a reference voltage source (VREF) through a reference resistance (RREF). The reference voltage source decreases each cell current (I) flowing through the line node by an average current (I−). Amplifiers (OPI, RG) convert the difference between the cell current and the average current into a voltage (VOUT) serving as an evaluation signal. The reference resistance (RREF) may be formed from interconnection of cell resistances of cells having different data. The reference resistance may have individual series connection of two cell resistances of cells having different data contents or parallel connection of the series connection.
Also, a magnetic random access memory having a reference memory array is disclosed in Japanese Laid Open Patent Application (JP-P2002-533863A) (International application No. PCT/US99/29310). The magnetic random access memory is provided with a first conductive line, a magnetic memory cell, a second conductive line, a reference magnetic memory cell, and a resistive element. The magnetic memory cell is connected with the first conductive line in series. The magnetic memory cell has a magnetic resistances switched between minimum magnetic resistance and maximum magnetic resistance in accordance with the direction of a stored magnetic vector. The reference magnetic memory cell is connected with the second conductive line in series, and has a predetermined magnetic resistance. The resistive element is connected with the reference magnetic memory cell in series. A total resistance of the reference magnetic memory cell and the resistive element is set between the minimum magnetic resistance and the maximum magnetic resistance. The resistive element may be set so that the total resistance takes an intermediate-point resistance between the minimum magnetic resistance and the maximum magnetic resistance.
In addition, a magnetic memory apparatus is disclosed in Japanese Laid Open Patent Application (JP-P2002-367364A). The magnetic memory apparatus has a memory cell, a word line, a bit line, a reference bit line, and an amplifier. The memory cell is provided with one memory element showing a ferromagnetic tunnel effect and one transistor connected to the memory element. The word line is connected to a control terminal of the transistor. The bit line is connected to one end of the memory element through the transistor. The reference bit line is provided in common to a plurality of the bit lines. The amplifier is connected to the bit lines and the reference bit line. Moreover, a voltage difference generated between the bit line and the reference bit line is read by the amplifier in a read operation of a data. A reference memory cell provided for each word line is provided for the reference bit line, and the reference memory cell includes one first resistive element and one transistor connected to the first resistive element. The first resistive element of the reference memory cell may have an intermediate value between a resistance value when the directions of magnetizations of the memory cell are parallel and a resistance value when the directions of magnetizations of the memory element are anti-parallel.
Furthermore, a magnetic random access memory is disclosed in Japanese Laid Open Patent Application (JP-P2002-196575A). This magnetic random access memory is provided with a cross-point cell array, a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction different from the first direction, a dummy bit line extending in the second direction, a first selector for selecting one of the plurality of word lines, a second selector for selecting one of the plurality of bit lines, and a read circuit. The plurality of word lines extend in a first direction. The plurality of bit lines extend in a second direction different from the first direction. The dummy bit line extends in the second direction. The first selector selects one of the plurality of word lines, and the second selector selects one of the plurality of bit lines. The cross-point cell array includes a plurality of cells. Each of the plurality of cells has reversible spontaneous magnetization and includes a tunneling magnetic resistance whose resistance differs in accordance with the direction of the spontaneous magnetization. The plurality of cells contains a plurality of memory cells for storing data in accordance with the direction of the spontaneous magnetization and a plurality of dummy cells. Each of the plurality of memory cells is provided between one of the plurality of word lines and one of the plurality of bit lines. Each of the plurality of dummy cells is provided between one word line of the plurality of word lines and the dummy bit line. The read circuit includes an offset removal circuit and a data determination circuit. The offset removal circuit generates a current difference signal corresponding to the difference between a detection current flowing through the selected word line when a voltage is applied between the selected word line and the selected bit line and an offset component current flowing through the dummy bit line when a voltage is applied between the selected word line and the dummy bit line. The data determination circuit determines the storage data stored in a selected cell provided between the selected word line and the selected bit line in accordance with the current difference signal.